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个人信息Personal Information
副教授
博士生导师
硕士生导师
教师英文名称：Xueqing Li
教师拼音名称：Li Xueqing
电子邮箱：xueqingli@tsinghua.edu.cn
学历：研究生(博士)毕业
办公地点：清华大学罗姆电子工程馆4304
性别：男
联系方式：+86-10-6278-0591
学位：博士学位
毕业院校：清华大学
个人主页：https://nics.ee.tsinghua.edu.cn/people/Xueqing/
- Taixin Li, Hongtao Zhong, Sumitha George, Vijaykrishnan Narayanan, Liang Shi, Huazhong Yang, and Xueqing Li, “Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays,” 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
- Hongtao Zhong, Yu Zhu, Longfei Luo, Chen Wang, Yixin Xu, Tianyi Wang, Yao Yu, Vijaykrishnan Narayanan, Yongpan Liu, Liang Shi, Huazhong Yang, and Xueqing Li, “Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks,” 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
- Yanan Sun, Dengfeng Wang, Liukai Xu, Yiming Chen, Zhi Li, Songyuan Liu, Weifeng He, Yongpan Liu, Huazhong Yang, and Xueqing Li, “CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration,” IEEE Transactions on Circuits and Systems I: Regular Papers
- Xiaoyang Ma, Shan Deng, Juejian Wu, Zijian Zhao, David Lehninger, Tarek Ali, Konrad Seidel, Sourav De, Xiyu He, Yiming Chen, Huazhong Yang, Vijaykrishnan Narayanan, Suman Datta, Thomas Kampfe, Qing Luo, Kai Ni, and Xueqing Li, "A 2-Transistor-2-Capacitor Ferroelectric Edge Compute-in-Memory Scheme with Disturb-Free Inference and High Endurance," IEEE Electron Device Letters
- Yiming Chen, Guodong Yin, Mufeng Zhou, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, and Xueqing Li, "SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity-Compensated Fully-Parallel Analog Adder Tree," IEEE TCAS-I.
- Jianfeng Wang, Zhonghao Chen, Yiming Chen, Yixin Xu, Tianyi Wang, Yao Yu, Vijaykrishnan Narayanan, Sumitha George, Huazhong Yang, and Xueqing Li, "WeightLock: a Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators," AICAS2023.
- Wenjun Tang, Mingyen Lee, Juejian Wu, Yixin Xu, Yao Yu, Yongpan Liu, Kai Ni, Yu Wang, Huazhong Yang, Vijaykrishnan Narayanan, Xueqing Li, "FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access with Reduced Bitline Charging Activity and Recycled Bitline Charge," IEEE TCAS-I.
- Mingyen Lee, Wenjun Tang, Yiming Chen, Juejian Wu, Hongtao Zhong, Yixin Xu, Yongpan Liu, Huazhong Yang, Vijaykrishnan Narayanan, and Xueqing Li, "Victor: A Variation-resilient Approach Using Cell-clustered Charge-domain computing for High-density High-throughput MLC CiM," DAC2023.
- Hongtao Zhong, Zhonghao Chen, Wenqin Huangfu, Chen Wang, Yixin Xu, Tianyi Wang, Yao Yu, Yongpan Liu, Vijaykrishnan Narayanan, Huazhong Yang, and Xueqing Li, "ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory," DAC2023.
- J. Yue, C. He, Z. Wang, Z. Cong, Y. He, M. Zhou, W. Sun, X. Li, C. Dou, F. Zhang, H. Yang, Y. Liu, M. Liu, "A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse Digital Architecture," ISSCC2023.
- Y. He, H. Diao, C. Tang, W. Jia, X. Tang, Y. Wang, J. Yue, X. Li, H. Yang, H. Jia, Y. Liu, "A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference," ISSCC 2023.
- Yushen Fu, Chengyu Huang, Longqiang Lai, Nan Sun, Xueqing Li*, and Huazhong Yang, "A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC Achieving >70dBc SFDR and <-80dBc IM3 up to 1GHz with Enhanced Constant-Switching-Activity Data-Weighted-Averaging," IEEE TCAS-I.
- Yushen Fu, Chengyu Huang, Limeng Sun, Weiguang Meng, Xueqing Li*, and Huazhong Yang, "A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration," IEEE TVLSI.
- Yiming Chen, Yushen Fu, Mingyen Lee, Sumitha George, Yongpan Liu, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li, "FAST: A Fully-Concurrent Access SRAM Topology for High Row-wise Parallelism Applications Based on Dynamic Shift Operations," IEEE TCAS-II.
- Yi Xiao, Yixin Xu, Zhouhang Jiang, Shan Deng, Zijian Zhao, Antik Mallick, Limeng Sun, Rajiv Joshi, Xueqing Li, Nikhil Shukla, Vijaykrishnan Narayanan, and Kai Ni, "On the Write Schemes and Efficiency of FeFET 1T NOR Array for Embedded Nonvolatile Memory and Beyond," IEDM 2022.