|
个人信息Personal Information
副教授
博士生导师
硕士生导师
教师英文名称：Xueqing Li
教师拼音名称：Li Xueqing
电子邮箱：
学历：研究生(博士)毕业
办公地点：清华大学罗姆电子工程馆4304
性别：男
联系方式：+86-10-6278-0591
学位：博士学位
毕业院校：清华大学
个人主页：https://nics.ee.tsinghua.edu.cn/people/Xueqing/
- Tianyi Yu, Tianyu Liao, Mufeng Zhou, Xiaotian Chu, Guodong Yin, Mingyen Lee, Yongpan Liu, Huazhong Yang, Xueqing Li, "DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level," ASP-DAC2025.
- Hongtao Zhong, Zijie Zheng, Leming Jiao, Zuopu Zhou, Chen Sun, Wenjun Tang, Zhonghao Chen, Vijaykrishnan Narayanan, Huazhong Yang, Thomas Kampfe, Kai Ni, Xiao Gong, Xueqing Li, "First Demonstration of AFeFET-Based Capacitor-Less eDRAM Computing-in-Memory Featuring 4.84 Mb/mm^2 High Memory Density, 10^5 s Long Retention Time, and >10^10 High Endurance," IEDM 2024.
- Jianfeng Wang, Huazhong Yang, Shuwen Deng, and Xueqing Li, "CiMSAT: Exploiting SAT Analysis to Attack Compute-in-Memory Architecture Defenses," 2024 ACM Conference on Computer and Communications Security (ACM CCS 2024).
- Haikang Diao, Yifan He, Xuan Li, Chen Tang, Wenbin Jia, Jinshan Yue, Haoyang Luo, Jiahao Song, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu, Yuan Wang, and Xiyuan Tang, "A Multiply-less Approximate SRAM Compute-In- Memory Macro for Neural-Network Inference," in IEEE Journal of Solid-State Circuits.
- Taixin Li, Hongtao Zhong, Yixin Xu, Vijaykrishnan Narayanan, Kai Ni, Huazhong Yang, Thomas Kampfe, and Xueqing Li, "REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive Control," ICCAD2024.
- Hongtao Zhong, Taixin Li, Yiming Chen, Wenjun Tang, Juejian Wu, Huazhong Yang, and Xueqing Li, "NAND-Tree: A 3D NAND Flash Based Processing In Memory Accelerator for Tree-Based Models on Large-Scale Tabular Data," ICCAD2024.
- Jialong Liu, Wenjun Tang, Deyun Chen, Chen Jiang, Huazhong Yang, and Xueqing Li, "Cross-Layer Exploration and Chip Demonstration of In-Sensor Computing for Large-Area Applications with Differential-Frame ROM-Based Compute-In-Memory," DAC2024.
- Liukai Xu, Shuai Yuan, dengfeng wang, Yiming Chen, Xueqing Li, and Yanan Sun, "HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-task Transformer Acceleration," DAC2024.
- Bowen Liu, Yangkun Hou, Yueshan Qin, Jiwei Zou, Hanbin Ma, Yongpan Liu, Huazhong Yang, Xueqing Li, and Chen Jiang, "A 1024-Channel Neurostimulation System Enabled by Photolithographic Organic Thin-Film Transistors with High Uniformity," ISCAS 2024.
- Chengyu Huang, Kezhuo Ma, Sihao Chen, Jiaxuan Fan, Nan Sun, Huazhong Yang, and Xueqing Li, “A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS,” in 2024 IEEE Custom Integrated Circuits Conference (CICC).
- Guodong Yin, Yiming Chen, Mingyen Lee, Xirui Du, Yue Ke, Wenjun Tang, Zhonghao Chen, Mufeng Zhou, Jinshan Yue, Huazhong Yang, Hongyang Jia, Yongpan Liu, and Xueqing Li, “A 28nm 8928Kb/mm2-weight-density hybrid SRAM/ROM Compute-in-Memory architecture reducing >95% weight loading from DRAM,” in 2024 IEEE Custom Integrated Circuits Conference (CICC).
- Jianfeng Wang, Zhonghao Chen, Jiahao Zhang, Yixin Xu, Tongguang Yu, Ziheng Zheng, Enze Ye, Sumitha George, Huazhong Yang, Yongpan Liu, Vijaykrishnan Narayanan, and Xueqing Li, “A Module-Level Configuration Methodology for Programmable Camouflaged Logic,” in ACM Transactions on Design Automation of Electronic Systems.
- Jialong Liu, Wenjun Tang, Hongtian Li, Deyun Chen, Weihang Long, Yongpan Liu, Chen Jiang, Huazhong Yang, and Xueqing Li, "TFT-Based Near-Sensor In-Memory Computing: Circuits and Architecture Perspectives of Large-Area eDRAM and ROM CiM Chips," IEEE TCAS-I.
- Jianfeng Wang, Shuwen Deng, Huazhong Yang, Vijaykrishnan Narayanan and Xueqing Li,"TroScan: Enhancing On-Chip Delivery Resilience to Physical Attack through Frequency-Triggered Key Generation," DATE2024.
- Taixin Li, Hongtao Zhong, Juejian Wu, Thomas Kampfe, Kai Ni, Vijaykrishnan Narayanan, Huazhong Yang and Xueqing Li, "CafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector Merging," DATE2024.